1. Technical Field
The present invention relates in general to a method and system for data processing and in particular to a method and system for executing instructions within a data processor. Still more particularly, the present invention relates to a method and system for executing branch instructions within a data processor utilizing software to direct hardware branch prediction mechanisms to take a particular path.
2. Description of the Related Art
A conventional high performance superscalar processor typically includes an instruction cache for storing instructions, an instruction buffer for temporarily storing instructions fetched from the instruction cache for execution, a number of execution units for executing sequential instructions, a Branch Processing Unit (BPU) for executing branch instructions, a dispatch unit for dispatching sequential instructions from the instruction buffer to particular execution units, and a completion buffer for temporarily storing instructions that have finished execution, but have not been completed.
As is well known in the art, sequential instructions fetched from the instruction queue are stored within the instruction buffer pending dispatch to the execution units. In contrast, branch instructions fetched from the instruction cache are typically forwarded directly to the branch processing unit for execution. The branch processing unit utilizes a prediction mechanism, such as a branch history table, to predict which execution path should be taken. If a branch is predicted taken, instructions at the target address of the branch instruction are fetched and executed by the processor. In addition, any sequential instructions following the branch that have been prefetched are discarded. However, the outcome of a branch instruction often cannot be determined prior to executing the branch instruction. In conventional processors, the dispatch of sequential instructions following a branch predicted as taken is halted and instructions from the speculative target instruction stream are fetched during the next processor cycle. If the branch that was predicted as taken is resolved as mispredicted, a mispredict penalty is incurred by the processor due to the time required to restore the sequential execution stream following the branch instruction; Similarly, if the branch that was predicted as not taken is resolved as mispredicted, a mispredict penalty is incurred by the processor due to the time required to fetch and execute from the target instruction stream.
A high performance processor achieves high instruction throughput by fetching and dispatching instructions under the assumption that branches are correctly predicted and allows instructions to execute without waiting for the completion of previous instructions. This is commonly known as speculative execution, i.e., executing instructions that may or may not have to be executed. The CPU guesses which path the branch is going to take. This guess may be a very intelligent guess (as in a branch history table) or very simple guess (as in always guess path not taken). Once the guess is made, the CPU starts executing that path. Typically, the processor executes instructions speculatively when it has resources that would otherwise be idle, so that the operation may be done at minimum or no cost. Therefore, in order to enhance performance, some processors speculatively predict the path to be executed after an unresolved branch instruction. Utilizing the result of the prediction, the fetcher then fetches instructions from the predicted path prior to the resolution of the branch, thereby avoiding a stall in the execution pipeline if the branch is resolved as correctly predicted. Thus, if the guess is correct, there are no holes in the instruction sequence or delays in the pipeline and execution continues at full speed. If, however, subsequent execution of the branch indicate that the branch was wrongly predicted, the processor has to abandon any result that the speculatively executed instructions produced and begin executing the path that should have been taken. The processor xe2x80x9cflushesxe2x80x9d or throws away the results of these wrongly executed instructions, backs itself up to get a new address, and executes the correct instructions.
Prior art handling of this speculative execution of instructions includes U.S. Pat. No. 5,454,117 which discloses a branch prediction hardware mechanism. The mechanism performs speculative execution based on the branch history information in a table. Similarly, U.S. Pat. No. 5,611,063 discloses a method for tracking allocation of resources within a processor utilizing a resource counter which has two bits set in two possible states corresponding to whether or not the instruction is speculative or when dispatched to an execution unit respectively. Also, Digital Equipment Corporation""s Alpha AXP Architecture includes hint bits utilized during its jump instructions. However, as the name implies, these bits are hint only and are often ignored by the jump mechanism.
Most operations can be performed speculatively as long as the processor appears to follow a simple sequential method, such as those in a scalar processor. For some applications, however, speculative operations can be a severe detriment to the performance of the processor. For example, in the case of executing a load instruction after a branch instruction (known as speculative load because the load instruction is executed speculatively without knowing exactly which path of the branch would be taken), if the predicted execution path is incorrect, there is a high delay penalty incurred when the pending speculative load in the instruction stream requests the required data from the system bus. In many applications, the rate of mis-predicted branches is high enough that the cost of speculatively accessing the system bus is prohibitively expensive. Furthermore, essential data stored in a data cache may be displaced by some irrelevant data obtained from the system bus because of a wrongful execution of a speculative load instruction caused by misprediction. A need, therefore, exists for improvements in branch prediction and speculative execution.
Presently, most prediction mechanisms operate as hardware prediction. These predicted paths, when mispredicted, tend to corrupt the hardware memory with the results of the speculatively executed instructions. However, certain classes of branches should not be predicted by hardware when the software can tell with a particular degree of certainty which path to take. Presently, no prior art discloses a processor method or system for utilizing software to directly control a hardware prediction mechanism. Consequently, a system and method for software controlled branch prediction mechanism is desired.
It would therefore be desirable to provide a method and system for combining software and hardware branch prediction in a high performance processor. It is further desirable to provide a method and system which allows a developer or compiler of a software code (or program) which has a pre-determined and/or desired path during branch prediction to control the actual path predicted by manipulating the hardware prediction mechanism with a software input.
It is therefore one object of the present invention to provide an improved method and system for data processing.
It is another object of the present invention to provide an improved method and system for executing instructions within a data processor.
It is yet another object of the present invention to provide a method and system for executing branch instructions within a data processor utilizing software to direct hardware branch prediction mechanisms to take a particular path.
The foregoing objects are achieved as is now described. A method and system for software manipulation of hardware branch prediction mechanism in a data processor is disclosed. The hardware branch prediction mechanism is enhanced with at least two bits for path prediction. These bits may be set by software and are capable of overriding the hardware branch prediction mechanism. Branch prediction information is encoded into a branch instruction in the software. This information includes a pre-determined value for each bit. Finally, a branch path of the instruction is predicted based on the value of the bits.
In one embodiment, a first bit is set to one of two possible values wherein a first value corresponds to hardware branch prediction and a second value corresponds to software branch prediction. The second bit is set to a value corresponding to the software prediction path desired.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.